The present invention relates to first-in-first-out (FIFO) semiconductor integrated circuit devices.
A FIFO is a buffer memory where data becomes available to the output port in the same order it was presented to the input port. One purpose of the present invention is to provide a bidirectional FIFO that can be directed according to the needs of the application and allow the user to drive through the device to program devices connected to the opposite bus.
There have been numerous prior approaches to the problem of a bidirectional FIFO. The most prevalent is to use two separate FIFO devices with associated control logic implemented in programmable logic devices. Recently, bidirectional FIFOs have appeared in silicon; however, these FIFOs offer a very complex approach in that two FIFOs are implemented "back-to-back." This is a very cumbersome and expensive way to solve the problem. Typically the user does not require simultaneous transfer of data in both directions; instead applications require FIFO data in one direction or the other at various times. Moreover, such approaches suffer the disadvantages of increased complexity and cost, and with adverse effects on the device speed. According to one aspect of the present invention, a single FIFO memory array whose directionality may be altered is utilized.
Another aspect of the present invention is to provide a means by which the user of the FIFO device can test the contents of the FIFO with no external circuits. Conventional FIFO designs require that the user add several external devices to the FIFO to allow the data previously written into the FIFO to be read out by the device that wrote the data. This conventional approach requires these additional devices and additional board space.
A further aspect of the present invention is to provide an alternate method of device-mode selection by means of control signal edge placement (skew). Previous or conventional devices have used methods such as extra control pins, encoded pin signals, clocking mode-information, and complex control protocols to provide additional modes of operation. Disadvantages of the conventional approaches include higher pin counts, increased complexity, or deviations from the standard or traditional operationality. Quite often, the user must learn a dramatically different functionality.